 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| KS7212 GENERAL DESCRIPTION TIMING & SYNC. GENERATOR FOR B/W CCD The KS7212 is a CMOS integrated circuit designed for making various timing pulses for B/W CCD camera. 48-QFP-0707 FEATURES - Compatible with both EIA and CCIR mode (EIA : KC73125(U)-M, CCIR : KC73129(U)-M) - Built in auto iris function (Electronic Exposure) - Mirror mode timing generation - Field interlace mode only - Timing and sync one chip IC - Oscillation frequency EIA : 19.06992MHz, CCIR : 18.93750MHz APPLICATION - B/W CCD Camera ORDERING INFORMATION Device KS7212 Package 48-QFP-0707 Operating Temperature -20~75C BLOCK DIAGRAM XSUB XSG1 XSG3 25 H4 H3 H1 H2 XV2 XV1 XV3 38 CL 43 X2 41 X1 40 TS2 45 37 36 35 33 30 29 28 27 26 24 22 SHP SHD XV4 RG 1/2 GATE1 21 1/606 Horizontal ROM F/F GATE2 18 17 16 15 14 13 CLP1 CLP2 CLP3 DFDO CLEN WIN TS1 46 TS0 47 PWR 48 1/525 or 1/625 High/Low Control Shutter Speed ROM Vertical ROM Shutter Speed Count F/F Shutter Speed Control 1 MD2 2 MD1 3 EE1 4 EE2 7 FLD 8 PBLK 9 CSYNC 10 CBLK 11 VD 12 HD KS7212 PIN DESCRIPTIONS No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol MD2 MD1 EE1 EE2 VSS1 VDD1 FLD PBLK CSYNC CBLK VD HD WIN CLEN DFDO CLP3 CLP2 CLP1 VSS2 VDD2 SHD SHP VSS3 XV4 XSG3 V3 XSG1 XV1 XV2 XSUB VDD3 VSS4 RG VDD4 H2 H1 H3 H4 VSS5 X1 X2 VDD5 CL VSS6 TS2 TS1 TS0 PWR TIMING & SYNC. GENERATOR FOR B/W CCD I/O I I I I O O O O O O O O O O O O O O O O O O O O O O O O O O I O O O I I I - Description CCIR/EIA mode selection NORMAL/MIRROR mode selection EE mode control input 1 EE mode control input 2 Ground +5V Field separation pulse Pre - blanking pulse Composite Sync.pulse Composite Blanking pulse Vertical driving pulse Horizontal driving pulse Window pulse 1/2 HD frequency pulse 1/2 VD frequency pulse Clamp pulse 3 (Dummy black level) Clamp pulse 2 (Optical black level) Clamp pulse 1 (Optical black level) Ground +5V Data Sample & Hold pulse Pre - Charge Sample & Hold pulse Ground Vertical transfer clock 4 Read out Pulse 3 Vertical transfer clock 3 Read out Pulse 1 Vertical transfer clock 1 Vertical transfer clock 2 Shutter speed control for auto Iris +5V Ground Reset gate pulse +5V Horizontal transfer pulse 2 ( Mirror mode) Horizontal transfer pulse 1 ( Normal mode' ) H' Horizontal transfer pulse 3 ( Normal mode' ) H2' Horizontal transfer pulse 4 ( Mirror mode ) Ground Oscillation clock Input EIA : 19,069928MIHz CCIR : 18.93750MHz Oscillation clock Output +5V 1/2 Oscillation clock EIA : 9.953496Mhz CCIR : 9.46875MHz Ground Test Input 2 Test Input 1 Test Input 0 Power On Reset Remark * Information (1) * Information (1) * Information (2) * Information (2) KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD Information 1) MD2 and MD1 mode selection ( Pull - down ) MD2 L H MD1 L H L H MODE EIA NORMAL EIA MIRROR CCIR NORMAL CCIR MIRROR Information 2 ) EE2 and EE1 shutter speed mode selection ( Pull- up ) EE2 L H EE1 L H L H MODE SHUTTER SPEED STOP SHUTTER SPEED UP SHUTTER SPEED DOWN SHUTTER SPEED STOP ABSOLUTE MAXIMUM RATINGS Characteristics Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Symbol VCC VI VO T OPR T STG Value 7 VSS-0.5 ~ VDD+0.5 VSS-0.5 ~ VDD+0.5 -20 ~ +75 -55 ~ +150 Unit V V V C C ELECTRICAL CHARACTERISTICS (VDD=5V, Ta=25C, unless otherwise specified) Characteristics Supply Voltage Input Voltage Output Voltage 1 Output Voltage 2 (CL, RG, SHP, SHD) Output Voltage 3 (H1, H2, H3, H4) Symbol VDD VIH VIL VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 Test Condition IOH1=-2mA ICL1=4mA ICH2=-4mA IOL2=3mA ICH3=-8mA ICL3=8mA Min 4.75 0.7VDD VDD-0.5 VDD-0.5 VDD-0.5 Typ 5.0 Max 5.25 0.3VDD 0.4 0.4 0.4 Unit V V V V V V V V V KS7212 AC CHARACTERISTICS tr TIMING & SYNC. GENERATOR FOR B/W CCD tf twh 90% 0.9VDD 10% twl 0.1VDD twh PULSES Min. XSG1 , XSG3 XV1 , XV2 , XV3 , XV4 H1 , H2 , H3 , H4 RG XSUB SHP , SHD , CLP1 , CLP2 , CLP3 , DFD0 , CLEN , WIN , HD , VD , CBLK , CSYNC , FLD 26 11 1.5 32 13 2.0 26 2.3 Typ. Max. Min. 2.5 twl Typ. Max. Min. tr Typ. Max. Min. 0.5 0.015 tf Unit Typ. Max. 0.5 0.24 12 11 5 0.5 0.5 12 us us ns ns us 32 51 11 5 13 14 16 13 14 16 ns KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD OPERATING PRINCIPLES & METHOD POWER ON RESET KS7212 has two reset methods. The one is power on reset and the other is normal reset. When user wants to use power on reset , which generates automatical reset signal that is needed to initialize the KS7212 internal system when power is on, user should be connect 1000pF capacitor at PWR ( pin 48 ) termial. Power on reset system has internal 100Kohm pull up resister. So , user can control reset signal timing when user changes value of capacitor , which is connected to PWR terminal. When user wants to use normal reset , user should be remove capacitor from PWR terminal , and supplies reset signal to PWR terminal. 48 KS7212 RESET SIGNAL 48 KS7212 1000pF 2.4 ~ 2.6 V 840ns Fig. 1 POWER ON RESET Fig. 2 NORMAL RESET When use u-Com system , reset signal can be should be larger than four times of CL clock. supplied three times and times of 1 signal KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD APPLICATION CIRCUIT ( EIA , NORMAL mode ) TO VERTICAL DRIVER TO CCD VDD 36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 19.0699MHz X-tal 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 KS7212 TIMING & SYNC GEN 20 19 18 17 16 15 14 13 VDD TO SIGNAL PROCESSOR * Application circuit for EIA : 19.06992MHz CCIR : 18.93750MHz normal mode KS7212 TIMING & SYNC. GENERATOR FOR B/W CCD HIGH SPEED TIMING RELATIONSHIP X1 H1 PG CCD OUT SHP SHD KS7212 CCD VERTICAL DRIVING PULSE TIMING DIAGRAM HD V1 V2 ODD V3 V4 V1 V2 EVEN V3 1.1uS 2.0uS V4 XSG1 39.5uS XSG2 43.5uS 2.5uS UNIT : S TIMING & SYNC. GENERATOR FOR B/W CCD 2.5uS KS7212 1/2H 6.36 HD 10.76 HBLK 4.89 1.47 HSYNC EQSYNC 2.45 26.89 4.86 VSYNC ODD VD EVEN VD FLD UNIT uS TIMING & SYNC. GENERATOR FOR B/W CCD KS7212 HORIZONTAL TIMING CHART FOR CCIR 1/2H 6.41 HD 11.70 HBLK 4.93 1.48 HSYNC EQSYNC 2.47 27.07 4.93 VSYNC ODD VD EVEN VD FLD UNIT uS TIMING & SYNC. GENERATOR FOR B/W CCD KS7212 HORIZONTAL TIMING CHART FOR MIRROR EIA MODE 1/2H 6.36 HD 10.76 HBLK 2.724 4.89 HSYNC EQSYNC 2.45 26.89 VSYNC 4.86 ODD VD CLP1 CLP2 CLP3 UNIT uS TIMING & SYNC. GENERATOR FOR B/W CCD KS7212 HORIZONTAL TIMING CHART FOR MIRROR CCIR MODE 1/2H 6.41 HD 11.70 HBLK 2.745 4.93 HSYNC EQSYNC 2.47 27.07 VSYNC 4.93 ODD VD CLP1 CLP2 CLP3 UNIT uS TIMING & SYNC. GENERATOR FOR B/W CCD KS7212 H1, H2, H3, H4, PG, SHP, SHD TIMING CHART AT MIRROR MODE OF CCIR OSC1 H1 H2 H3 H4 PG SHP TIMING & SYNC. GENERATOR FOR B/W CCD SHD KS7212 EIA VERTICAL TIMING CHART FIELD E FIELD O HD 9H VD CSYNC 20H CBLK FLD 80H WIN FIELD O FIELD E HD 9H VD CSYNC 20H CBLK FLD 80.5H TIMING & SYNC. GENERATOR FOR B/W CCD WIN KS7212 CCIR VERTICAL TIMING CHART FIELD E FIELD O HD 7.5H VD CSYNC 25H CBLK FLD 97H WIN FIELD O FIELD E HD 7.5H VD CSYNC 25H CBLK FLD 96.5H TIMING & SYNC. GENERATOR FOR B/W CCD WIN KS7212 VERTICAL TIMING CHART FOR EIA FLD VD BLK HD 10 15 20 25 520 5 4 3 2 1 525 270 265 260 275 280 285 290 XSG1 XSG2 V1 V2 V3 V4 24 6 246 135 1 35 491 492 492 493 13 5 246 1357 2 46 8 CCD OUT CLP1 CLP2 CLP3 TIMING & SYNC. GENERATOR FOR B/W CCD PBLK KS7212 VERTICAL TIMING CHART FOR CCIR FLD VD BLK HD 335 10 15 20 25 340 620 5 4 3 2 1 625 320 315 310 325 330 XSG1 XSG2 V1 V2 V3 V4 24 6 246 135 135 135 582 583 246 CCD OUT CLP1 CLP2 CLP3 PBLK TIMING & SYNC. GENERATOR FOR B/W CCD 582 581 13 5 7 24 68 KS7212 PACKAGE DIMENSION 48-QFP-0707 TIMING & SYNC. GENERATOR FOR B/W CCD unit : mm 9.00 + 0.30 - 7.00 + 0.20 - 0~ 8 0.1 3+ 0 - 0 .10 .05 9.00 - 0.30 + 7.00 - 0.20 + 0.10 MAX # 48 #1 0.18 + 0.10 - 0.50 0.10 MAX ( 0.75 ) 0.00 MIN 1.40 + 0.10 - 1.60 MAX 0.50 - 0.20 + |
Price & Availability of KS7212
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |